An integrated circuit is commonly comprised of a circuit chip and a package, and called semiconductor device package by the Man skilled in electronic circuit manufacturing.
The circuit chip includes a semiconductor substrate which has an upper substrate surface, and further includes several interconnect layers which are stacked on the upper substrate surface. The upper substrate surface and the upper stack surface are both generally perpendicular to a stacking direction of the integrated circuit. The substrate incorporates electrically doped regions having electrical resistivity values of less than 10 Ohm·cm, which form parts of electronic components of the circuit. Metal tracks and vias are formed on and through the interconnect layers, respectively, which are configured for electrically connecting the electronic components.
Bond pads are located at an upper layer surface of the layer stack opposite the semiconductor substrate. The bond pads are electrically connected to some of the tracks and vias at one end, and to external electrical contacts of the circuit on the other end.
One function of the package is to spatially redistribute the bond pads to or from the electrical contacts. The electrical contacts allow the mounting of the integrated circuit on an external support, such as a printed circuit board (PCB) or a low-temperature co-fired ceramic (LTCC) used as a circuit support.
Several technologies have been developed for the package. A widely used technology is the so-called redistributed chip package (RCP). After a semiconductor wafer has been processed for producing the electronic components and the stack of interconnect layers, it is cut into separate pieces, each forming a circuit chip. The circuit chips are then individually embedded into a respective RCP module. The electrical contacts of the RCP module for connection to the external support are distributed according to a fan-out design wherein the contacts to the external support are located externally around the circuit chip in a top view of the module. Thanks to such design, there is almost no capacitive interaction between the chip and the electrical contacts of the RCP module to the external support. But the resulting integrated circuit is significantly larger than the circuit chip and requires corresponding available surface on the external support. Additionally, individually embedding each circuit chip into a respective RCP module causes significant manufacturing cost.
An alternative technology to RCP is that called wafer level chip scale package (WLCSP). The wafer level chip scale package is located on the upper stack surface of the circuit chip opposite the semiconductor substrate. It incorporates a plurality of under-bump metallization areas each provided with a respective solder ball. The solder balls are dedicated for connecting the integrated circuit to an external support. The wafer level chip scale package further incorporates electrically conducting segments which extend parallel to the upper stack surface. These electrically conducting segments each connect at least one of the bond pads to at least one of the under-bump metallization areas.
An advantage of the WLCSP technology is that the package is produced for the whole wafer at one time before the wafer is cut into separate circuit chips. The package is produced by implementing material layer deposition and selective etching steps over the entire wafer area. These deposition and etching steps include forming of polyimide layers, forming of the electrically conducting segments and forming of the under-bump metallization areas. Then, the cutting step directly produces the integrated circuits each already provided with its wafer level chip scale package.
According to a usually implemented layout for integrated circuit chips, the layers are delimited by a seal ring at the periphery of the chip. Then, the bond pads are arranged together with associated devices along the seal ring, on the inner side of the seal ring with respect to the external chip limit, for protection against electrostatic discharge (ESD). The electrically conducting segments within the wafer level chip scale package extend at least partially in one direction opposite the external chip limit, so that the under-bump metallization areas are shifted towards a center zone of the chip, in projection within the upper stack surface. Because of such inwardly shifted location of each under-bump metallization area with respect to the bond pads, the under-bump metallization areas are situated above functional blocks in the chip. Such functional blocks are circuit parts designed in the substrate and in the layers, which can be dedicated to specific functions such as signal processing and amplification, for example. When the electrical contact at each under-bump metallization area is dedicated to power supply, grounding or low-frequency signal transmission, no problem arises from the under-bump metallization area being above the circuit block. But when the under-bump metallization area is dedicated to transferring signals having a frequency higher than 30 GHz (gigahertz), for example, capacitive interactions can occur between electrically conducting parts of the circuit block and the under-bump metallization area. These interactions are nearly equivalent to short circuits for signals at such high frequency values, and may disturb the operation of the circuit.